1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to the formation of a wiring layer of a semiconductor device having a large base step in the layers under the wiring layers.
2. The Related Art
A semiconductor element which constitutes a semiconductor device is miniaturized and increased in density so as to heighten the integration of the semiconductor device. The formation of a multilayer wiring layer is an important technique for the higher integration of the semiconductor device. In particular, the formation of the multilayer wiring is becoming an important factor which affects the yield of good semiconductor devices. This affect occurs due to an unevenness of an interlayer insulating film on which the wiring layer formed. The unevenness of the interlayer insulating film is becoming very large making it difficult to control for the formation of the wiring layer in the photolithography process and in the dry etching process. Such unevenness of the interlayer insulating film results from a large base step of layers below the interlayer insulating film.
The base step under wiring layers has become quite remarkable in DRAMs of recent years because a DRAM memory cell typically has a stacked capacitor structure, and the height of a memory cell storage capacitor storage electrode and plate electrode increases with an increase in the volume of DRAM.
Conventional examples of the aforementioned DRAM will be explained by referring to FIGS. 5 and 6 which show an example in which a wiring layer is arranged on memory cells having stacked capacitors (hereinafter referred to as a first conventional example). Here, FIG. 5 is a plane view showing a corner part of memory cell array region. FIG. 6 is a sectional view of the memory cell region lined by II-II' of FIG. 5.
As shown in FIG. 5, the memory cell information storage electrode patterns 101a, 101b, 101c, 101d, 101e and 101f are formed in a matrix configuration. These memory cell capacitor storage electrode patterns are formed in a corner part area of a memory cell array of the DRAM. Then, a cell plate 102 is formed on the capacity insulating film 110 which will be described later. Furthermore, wiring layers 103a, 103b, 103c, 103d, 103e, 103f and the like are formed over a peripheral area and the memory cell array portion of the memory device on the interlayer insulating film 111. Here, as will be explained later, steps are formed between such memory cell array portion and the peripheral area surrounding the memory cell array portion.
As shown in FIG. 6, a field oxide film 105 is selectively formed on a surface of a P-type conductive type silicon substrate 104. Then a diffusion layer 106 having an N-type conductive type is formed on the surface of the silicon substrate 104. A first interlayer insulating film 107 covers the overall surface of the silicon substrate. Next, in a predetermined area, a contact hole 108 is provided which reaches the diffusion layer 106.
Then the memory cell capacitor information storage electrode 109, as a lower electrode, is connected to the diffusion layer 106 through the contact hole 108. On the surface of the memory cell capacitor information storage electrode 109 and on the surface of the interlayer insulating film 107, the capacitor insulating film 110 is formed. Furthermore, the cell plate 102, as an upper electrode of the memory cell capacitor, is formed on the capacitor insulating film 110. A second insulating film 111 covers the overall surface of the cell plate 102. Here, with an increase in the capacity of the DRAM the planar size of the memory cell capacitor information storage electrodes 101a, 101b, 101c, 101e, 101f, and the like, are reduced so that the height of the electrode 109 needs to be increased to ensure a predetermined storage capacitance value. As shown in FIG. 6, a large base step height is formed in the memory call device at the outside portion of the memory cell array area abutting the peripheral area surrounding the memory cell array area.
Then the second interlayer insulating film 111 is smoothed by means of heat treatment or the like. Furthermore, the metal film deposited on the second interlayer insulating film 111 is dry etched in patterns with a resist mask 112 which is formed using a photolithography process to form a wiring layer 103.
However, as shown in FIG. 7, when the base step height becomes large, a metal residual 113 remains between wiring layers, or in a space of wires. That is, this metal residual 113 is formed at the bend in the leg of a base step on the surface of the second interlayer insulating film 111 and causes a short circuit. The second interlayer insulating film 111 is steep and the film thickness of the wiring layer 103 at a step portion, labeled a, becomes, for example, two times or more as thick as the film thickness at the flat portion, labeled b, in FIG. 6. In the same manner, the film thickness at the step portion, labeled c, of the resist mask 112 becomes large as compared with the resist mask thickness at the flat portion, labeled d, as shown in FIG. 6.
On the other hand, if a long etching time is used to completely etch and remove the area of a large film thickness at the portion a by the dry etching process of the metal film 103, the etching time for the wiring layer 103 at the flat portion b becomes longer than required with the result that the wiring layers in the flat area are over-etched, for example, side etched such that layer 111 is etched undesirably. Furthermore, after formation of the resist mask 112 during the photolithography process, a long exposure time is required to completely remove the area c due to its large film thickness. However, the exposure time at the flat part d with a small film thickness is so long that the pattern width of the resist mask in the flat area becomes smaller.
A method for solving such problems as illustrated for the first conventional example will be explained hereinbelow. One such technique is described as the second conventional example while referring to FIGS. 8 and 9. FIG. 8 is a plane view showing a corner portion of a memory cell array and a peripheral area located adjacent to and the memory cell array area. FIG. 9 is a sectional view showing a stacked capacitor part for a cross section taken at line III-III'. Here, the same parts explained in the first conventional example are denoted by the same reference numerals.
In the same manner as the first conventional example, as shown in FIG. 8, the memory cell storage capacitor information storage electrode patterns 101a, 101b, 101c, 101d, 101e, 101f and the like are formed in a matrix configuration. Then, a cell plate 114 (storage capacitor second electrode) is formed on the capacitor insulating film 110. Furthermore, the wiring layers 103a, 103b, 103c, 103d, 103e, 103f are arranged on such memory cell part so as to run on the peripheral area of the memory cell area. Here, on the cell plate 114 a projecting parts 114a and 114b are formed in a definite cycle. Such projecting parts which are formed in a definite cycle provide an advantage which will be described later.
In the same manner as the first conventional example, a field oxide film 105 is formed on the surface of the silicon substrate shown in FIG. 9. Then, the diffusion layer 106 is formed on the surface of the silicon substrate 104, and an overall surface of the silicon substrate is covered with the first interlayer insulating film 107. Furthermore, a contact hole 108 is provided which reaches a definite area of the diffusion layer 106.
Furthermore, a memory cell storage capacitor information storage electrode 109 connected to the diffusion layer 106 via the aforementioned contact hole 108 is provided. Then, on the surface of the information storage electrode 109 and on the surface of the first interlayer insulating film 107, a capacitor insulating film 110 is formed. Furthermore, the cell plate 114 is formed on the capacitor insulating film 110, and an overall surface of the cell plate 114 is covered with the second interlayer insulating film 111. The second interlayer insulating film 111 is then smoothed with heat treatment. Furthermore, a metal film is deposited on the smoothed second interlayer insulating film 103 and dry etched in patterns with the resist mask so that the wiring layer 103 is formed.
The projecting part 114a of the cell plate 114 smoothes an inclination of the surface of the second interlayer insulating film 111 at the step. Then, when the wiring layer 103 is formed, the generation of the metal residual between the wiring layers as explained in the first conventional example, in this case, between the wiring layers 103c and 103d is almost prevented. Furthermore, the projecting parts 114a and 114b of the cell plate also smooth an inclination of the surface of the second interlayer insulating film 111 on the area sandwiched between these projecting parts 114a and 114b. As a consequence, the wiring layers 103e and 103f shown in FIG. 8 are arranged without the formation of the metal residual between the wiring layers 103e and 103f.
However, this conventional technique has the following problems. The problem which was discussed with reference to the first conventional example still occurs in the corner part area of the memory cell portion of the second conventional example. In other words, as illustrated in FIGS. 8 and 9, the wiring layer 103a arranged at the far most ends (four corners) of the memory cell array, i.e., the corner area of the memory cell array, the inclination angle and the step height part of the surface of the second interlayer insulating film 111 still remains large. As a consequence, accurately forming the wiring layer 103a arranged on the far most end of the memory cell array is difficult. For example, a short-cut is produced between the wirings 103a and 103b. Such problem becomes apparent along with increased planar area reduction of the design size of the semiconductor device and the memory cell of the memory cell array.